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Single event upset susceptibility testing of the Xilinx Virtex II FPGA

NASA NTRS · Conference Paper · 20060030120 · Published 2018-06-07 · Jet Propulsion Laboratory · 3 authors

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Abstract and citation only, verbatim from NASA NTRS; full text lives there. All credit to the authors and Jet Propulsion Laboratory.

Abstract

Heavy ion testing of the Xilinx Virtex IZ was conducted on the configuration, block RAM and user flip flop cells to determine their single event upset susceptibility using LETs of 1.2 to 60 MeVcm^2/mg. A software program specifically designed to count errors in the FPGA is used to reveal L1/e values and single-event-functional interrupt failures.

Authors

  • Yui, C.
  • Swift, G.
  • Carmichael, C.

Keywords

  • FPGA Xilinx Virtex static test single event upset

Citation

Yui, C., Swift, G., Carmichael, C. (2018). Single event upset susceptibility testing of the Xilinx Virtex II FPGA. Jet Propulsion Laboratory. NASA NTRS ID 20060030120. https://ntrs.nasa.gov/citations/20060030120 ↗