Skip to content

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

NASA NTRS · Conference Paper · 20060043759 · Published 2019-07-12 · Jet Propulsion Laboratory · 2 authors

Abstract and citation only, verbatim from NASA NTRS; full text lives there. All credit to the authors and Jet Propulsion Laboratory.

Abstract

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

Authors

  • Irom, Farokh
  • Farmanesh, Farhad H.

Keywords

  • single event upset (SEU)
  • microprocessors

Citation

Irom, Farokh, Farmanesh, Farhad H. (2019). Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors. Jet Propulsion Laboratory. NASA NTRS ID 20060043759. https://ntrs.nasa.gov/citations/20060043759 ↗